An FPGA Based Efficient Hardware Software Co design Architecture for ANN. Part 1(Abstraction)
Dear Reader,
I want to share my B.Tech Project Experience step by step via Series of Blog Posts.
Our B.Tech Final Year Project is on Artificial Neural Networks(ANN). So If you want are going to work on any project/work related to the ANN please do comment any of your doubts or clarifications.
This post is just any introduction to the project via the abstraction.
Project Title : An FPGA Based Efficient Hardware Software Co-Design Architecture for Artificial Neural Networks.
In this Title you may wonder what does FPGA means. If you want to know details about FPGA I will write a blog post about it, But do comment your opinion for that. But for now FPGA stands for simply Field Programmable Gate Array(FPGA).
This Project went for around 10-12 months with 6 hours a week and we are 5 member group.
Here is the abstraction for the project below.
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******Abstraction************
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Artificial neural networks (ANNs, or simply NNs) are inspired by biological nervous systems and consist of simple processing units (artificial neurons) that are interconnected by weighted connections. Neural networks can be “trained” to solve problems that are difficult to solve by conventional computer algorithms. The development of hardware platforms for neural networks has been complicated by the high hardware cost and quantity of the arithmetic operations required in an online MLP (Multi Layer Perceptron), i.e., one used to solve real-time problems. The challenge is thus to find an architecture that minimizes hardware costs while maximizing performance, accuracy, and parameterization. This project presents the hardware architecture for Artificial Neural Networks implemented on FPGA. In contrary to the traditional pure hardwired architectures that are rigid, our architecture emphasizes on software-hardware co-design bringing flexibility into the control path of the hardware. The architecture uses Altera’s NIOS II embedded soft processor as control unit and configured in CYCLONE-IV FPGA (EP4CE115F29C7N). The ISA of Nios II processor has extended with additional instructions for which computes the arithmetic required for the neural network. The design is implemented on FPGA and the performance improvements are measured.
For More information regarding this project Click Here.
If any Link is broken in this site please report us regarding it.
Click on Below Links to know regarding how to report.
[Link1] [Link2]
I want to share my B.Tech Project Experience step by step via Series of Blog Posts.
Our B.Tech Final Year Project is on Artificial Neural Networks(ANN). So If you want are going to work on any project/work related to the ANN please do comment any of your doubts or clarifications.
This post is just any introduction to the project via the abstraction.
Project Title : An FPGA Based Efficient Hardware Software Co-Design Architecture for Artificial Neural Networks.
In this Title you may wonder what does FPGA means. If you want to know details about FPGA I will write a blog post about it, But do comment your opinion for that. But for now FPGA stands for simply Field Programmable Gate Array(FPGA).
This Project went for around 10-12 months with 6 hours a week and we are 5 member group.
Here is the abstraction for the project below.
-----------------------------------------
******Abstraction************
-----------------------------------------
Artificial neural networks (ANNs, or simply NNs) are inspired by biological nervous systems and consist of simple processing units (artificial neurons) that are interconnected by weighted connections. Neural networks can be “trained” to solve problems that are difficult to solve by conventional computer algorithms. The development of hardware platforms for neural networks has been complicated by the high hardware cost and quantity of the arithmetic operations required in an online MLP (Multi Layer Perceptron), i.e., one used to solve real-time problems. The challenge is thus to find an architecture that minimizes hardware costs while maximizing performance, accuracy, and parameterization. This project presents the hardware architecture for Artificial Neural Networks implemented on FPGA. In contrary to the traditional pure hardwired architectures that are rigid, our architecture emphasizes on software-hardware co-design bringing flexibility into the control path of the hardware. The architecture uses Altera’s NIOS II embedded soft processor as control unit and configured in CYCLONE-IV FPGA (EP4CE115F29C7N). The ISA of Nios II processor has extended with additional instructions for which computes the arithmetic required for the neural network. The design is implemented on FPGA and the performance improvements are measured.
For More information regarding this project Click Here.
If any Link is broken in this site please report us regarding it.
Click on Below Links to know regarding how to report.
[Link1] [Link2]
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